Failsafe interface circuit

ABSTRACT

A fail-safe interface circuit comprises at least one semiconductor switching circuit (1) with a first link terminal (2), a second link terminal (4) and a control terminal (6). To connect a first and second circuit (8, 10) attached to the first and second link terminal (2, 4), respectively, a potential difference between the control terminal (6) and one of the link terminals (2, 4) is raised above a predetermined threshold value. To avoid any flow of current from the second circuit (10) to the first circuit (8) or vice versa when the interface circuit is powered off, the maximum potential at the first and second link terminal (2,4) is actively fed back to the control terminal (6) of the semiconductor switching circuit (1).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an failsafe interface circuit for theinput and output of digital signals and a method for the failsafeoperation of an interface circuit.

Currently, a variety of concepts for digital interface logic circuitryis known. Early concepts are diode-transistor logic DTL,transistor-transistor logic TTL and emitter coupled logic ECL whichconcepts are used with digital logic circuits as well as digitalsignaling between circuits and circuit boards.

Further approaches are based on MOS-processes (metal oxide semiconductorprocesses) which allow for advantages as higher packaging density orlower power consumption. Due to these advantages the MOS-processes noware widely used for very large scale integrated circuits such assemiconductor memories, microcomputers and circuits for the digitalsignal processing.

In particular the so called CMOS-technology wherein MOS-transistors ofboth the n-channel type and the p-channel type, i.e. PMOS-transistorsand NMOS-transistors are integrated on a single chip has been proven tobe extremely useful for such applications. One reason is that thecombination of PMOS- and NMOS-transistors allows to achieve almost nozero signal current and a significantly reduced power loss.

Further, the transfer characteristics of circuits constituting switchingcircuits can be very steep in case PMOS- and NMOS-transistors areactuated reciprocally. The CMOS-technology allows for a relatively lowoutput resistance defined through the resistance of the drain sourcepath of the respective PMOS- and NMOS-transistors. This is a furtherreason why CMOS-technology has gained significant importance for thedesign of digital circuitry.

Typical applications are interface circuits for the transmission ofdigital data with a high transfer rate, e.g., the differentialtransmission and reception of digital data using a pair of transmissionlines. Here, approaches like differential positive emitter coupled logicDPECL, low voltage differential signaling LVDC and grounded low voltagedifferential signaling GLVDS are used. All these approaches usedifferential signaling to keep differential voltages across a pair oftransmission lines as low as possible. This in turn keeps the power tobe transmitted over these transmission lines having low impedanceswithin reasonable limits.

DESCRIPTION OF PRIOR ART

FIG. 18 shows an example for an interface circuit well suited for suchapproaches and consisting of a power supply section 400 comprising aninductance 402, one PMOS-transistor 404, and one NMOS-transistor 406.Further, the output terminals of the power supply sections are connectedto the input terminals of a switching section 408 comprising two pairsof PMOS- and NMOS-transistors, each pair constituting a switchingcircuit 410, 412, respectively. These switching circuits are connectedto two input terminals of an output section 414 again comprising twopairs of PMOS- and NMOS-transistors 416 and 418 that can be used toselectively apply the potential at the input terminals of the outputsection 414 to an output terminal 420. This output terminal is connectedto, e.g., one line of a pair of transmission lines.

The interface circuit shown in FIG. 18 is used to output digital signalson symmetrical low impedance transmission lines or two asymmetric lowimpedance transmission lines. To this end the reactance circuit receivesenergy from a voltage source while the PMOS- and NMOS-transistor pairs410 and 412 forward this stored energy to the output section 414 duringa discharge phase. By means of appropriately setting the duration of thecharging phase and the discharging phase, it is possible to provide theoutput section 414 with a supply voltage suitable for power efficientoperation without dissipating large amounts of power and thus withoutgenerating a large amount of heat. This is a prerequisite forintegrating such interface circuits into a single CMOS integratedcircuit.

One problem with such interface circuits is that they are not failsafe.In particular, in case the interface circuit connected to thetransmission line is powered off or its supply section is powered offany current to or from the output terminal 420 must be avoided toachieve a strict decoupling of different sections in the interfacecircuit. If some or all sections comprise PMOS-transistors the supplyvoltage equals ground potential when the interface circuit is poweredoff. As soon as the drain or source electrodes of PMOS-transistors havea higher potential than the respective control electrodes thesePMOS-transistors are turned on and backward currents I3-I6 begin to flowthrough these PMOS-transistors. This, however, harms the free floatingfunction of the overall transmission system where it is assumed thatpowered off interface circuits are connected with a high impedance tothe transmission lines.

An additional problem with respect to this type of interface circuit isthe so called latchup phenomenon inherent to the CMOS-technology andillustrated in FIG. 19 and 20.

CMOS-technology requires the formation of both NMOS- andPMOS-transistors on a single substrate. Further, one possibility toisolate transistors against a substrate is the embedding of thesetransistors in insulating regions, e.g., the N-well 422 shown in FIG.19.

This, however, leads to the formation of parasitic diodes 424 to 434between semiconductor regions of a different conductivity type and thusalso to the formation of parasitic bipolar devices of the PNP-type 436and the NPN-type 438. As is shown in FIG. 20, the parasitic bipolardevices can form a four layer PNPN thyristor structure. If thisthyristor structure is turned on, the interface circuit destroys itselfby a conduction which is known as latchup phenomenon.

To avoid this latchup phenomenon the N-well and the spacings between thesource/drain regions of the different MOS-transistors must be carefullychosen to minimize the current gain of the parasitic bipolar transistors436, 438. In addition, it is necessary to control parasitic diodesbetween the source/drain regions of the transistors and the N-well sothat they are not forward biased. One approach is to apply the highestpotential in the interface circuit to the N-well of thePMOS-transistors.

However, while such an approach usually avoids the latchup phenomenon inan interface circuit it will not work when a source or drain electrodeof a PMOS-transistor is externally connected to, e.g., a transmissionline with a positive potential when the interface circuit is poweredoff. Under such a condition a current will flow from the externaltransmission line via the drain or source electrode of thePMOS-transistor and the parasitic diode to the N-well 422 connected tothe internal supply potential.

In other words, in known interface circuits it is impossible to controlthe potential of insulating well regions in case the interface circuitis powered off. However, this leads to a backward feed current viaparasitic diodes.

SUMMARY OF THE INVENTION

In view of the above, the object of the present invention is to providean interface circuit which is failsafe when the interface circuit ispowered off.

Thus, according to the present invention a failsafe interface circuitcomprises at least one semiconductor switching circuit with a first linkterminal, a second link terminal and a control terminal. To connect afirst and second circuit attached to the first and second link terminal,respectively, a potential difference between the control terminal andone of the link terminals is raised above a predetermined thresholdvalue. When the interface circuit is powered off, the maximum potentialat the first and second link terminal is actively fed back to thecontrol terminal in case the interface circuit or one of the first andsecond circuits is powered off.

Thus, according to the present invention, a failure in the interfacecircuit where a semiconductor switching circuit is turned on when theinterface circuit is powered off is safely prevented since in this casethe control terminal is disconnected from the related control logic andfollows the highest potential in the interface circuit.

According to a preferred embodiment of the invention there is provided afailure prevention circuit adapted to apply the maximum potential of thefirst link terminal and the second link terminal to an insulating regionof the semiconductor switching circuit when the failsafe interfacecircuit is powered off.

Therefore, no backward feed or latchup phenomenon occurs and no currentflows in parasitic diodes of the semiconductor switching circuit whenthe interface circuit is powered off. Also, a turning on of a parasiticthyristor formed by such parasitic diodes can be prevented effectivelysince the potential of all insulation regions are actively controlled tothe most positive potential in the failsafe interface circuit both whenthe power supply is turned on and when the power supply is turned off.

According to a further preferred embodiment of the invention thefailsafe interface circuit comprises a power supply section and adifferential output section. This allows to provide differential signalswhile keeping differential voltages across pairs of signal transmissionlines low without any adverse effect on the quality of datatransmission. Since the differential signaling approach leads to a lowpower dissipation per unit area an integration into a singleCMOS-circuit is possible since precautions are taken to avoid anybackward phenomenon or latchup phenomenon in the integrated interfacecircuit.

Embodiments of the present invention are described in the followingdescription in conjunction with the accompanying drawing in which:

FIG. 1 shows a semiconductor switching circuit for the failsafeinterface circuit;

FIG. 2 shows a further semiconductor switching circuit for the failsafeinterface circuit;

FIG. 3 shows a further semiconductor switching circuit embedded in aninsulating region;

FIG. 4 shows a further semiconductor switching circuit embedded in aninsulating region;

FIG. 5 shows a maximum generating circuit for generating a maximumpotential from two input potentials;

FIG. 6 shows a further maximum generating circuit for generating amaximum potential from two input potentials;

FIG. 7 shows an enhanced version of a maximum generating circuit forgenerating the maximum potential of two input potentials;

FIG. 8 shows a failsafe version of the maximum generating circuit shownin FIG. 7;

FIG. 9 shows a selector circuit to switch the maximum of two inputpotentials to an output terminal;

FIG. 10 shows a failsafe version of the selector circuit shown in FIG.9;

FIG. 11 shows a failsafe interface circuit applied to differentialtransmission of digital data;

FIG. 12 shows a further failsafe interface circuit applied todifferential transmission of digital data;

FIG. 13 shows a modification of the failsafe interface circuit shown inFIG. 12;

FIG. 14 shows a further failsafe interface circuit applied totransmission of digital data wherein switching noise can be efficientlycompensated for;

FIG. 15 shows a further failsafe interface circuit applied todifferential transmission of digital data wherein switching noise can beefficiently compensated for;

FIG. 16 shows a modification for the arrangement of the maximumgenerating circuits shown in FIG. 15;

FIG. 17 shows a differential output section substituting the outputsection of the failsafe interface circuit shown in FIG. 11;

FIG. 18 shows a known interface circuit applied to differentialtransmission of digital data which is not failsafe;

FIG. 19 shows parasitic diodes in a CMOS-circuit; and

FIG. 20 shows the formation of a parasitic thyristor structure in aCMOS-circuit.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 shows a first embodiment of the failsafe interface circuit thatis realized with a PMOS-transistor 1 that has a drain electrode 2, asource electrode 4 and a control electrode 6. Another possibilitydiscussed below is to couple an additional NMOS-transistor across thePMOS-transistor 1 to increase the operative range of the semiconductorswitching circuit.

The PMOS-transistor connects a first circuit 8 and a second circuit 10when a potential difference between either the control electrode 6 anddrain electrode 2 or the control electrode 6 and the source electrode 4exceeds a predetermined threshold value. Therefore, a suitable controlpotential is supplied to the control electrode 6 to switch thePMOS-transistor 1 on when the first circuit 8 must be connected to thesecond circuit 10.

With known interface circuits a particular problem arises during poweroff, i.e. when a low potential is supplied to the control electrode 6 ofthe PMOS-transistor 1. In case one of the first and second circuit 8, 10supplies a high potential to either the drain electrode 2 or the sourceelectrode 4 of the PMOS-transistor 1 a potential difference between thedrain electrode 2 or the source electrode 4 and the control electrode 6of the PMOS-transistor 1 is higher than the turn on threshold voltagethereof so that the interface circuit connects the first and secondcircuit 8, 10 also when it is powered off.

To avoid this problem, according to the present invention it is proposedto provide a conduction prevention circuit adapted to apply the maximumpotential of the drain electrode 2 and the source electrode 4 of thePMOS-transistor 1 to its control electrode 6 when the failsafe interfacecircuit is powered off.

The conduction prevention circuit comprises a maximum generating circuit12 that generates the maximum of the potential at the drain electrode 2and the source electrode 4 of the PMOS-transistor 1. The outputpotential of the maximum generating circuit 12 is supplied to a selectorcircuit 14 having three input terminals 16, 18, and 20 and one outputterminal 22 being connected to the control electrode 6 of thePMOS-transistor 1.

The first input terminal 16 receives a signal indicating that thefailsafe interface circuit is powered off, e.g. the supply potential ofthe interface circuit. The second input terminal 18 receives the normalcontrol potential for the control electrode 6 of the PMOS-transistor 1supplied via the output terminal 22 in case the failsafe interfacecircuit is powered on. Further, when the signal received via the inputterminal 16 indicates that the failsafe interface circuit is powered offthe selector circuit 14 switches from the input terminal 18 supplyingthe normal control potential to the input terminal 20 receiving theoutput potential of the maximum generating circuit 12, i.e. the maximumpotential of the drain electrode 2 and the source electrode 4 of thePMOS-transistor 1.

Therefore, when the failsafe interface circuit is powered off always themaximum potential of the drain electrode 2 and the source electrode 4 isactively supplied to the control terminal 6 of the PMOS-transistor 1.Thus, a failure in the interface circuit is safely prevented since thecontrol electrode 6 of the PMOS-transistor 1 is disconnected from thecontrol logic when the failsafe interface circuit is powered off andfollows the highest potential of the drain electrode 2 and the sourceelectrode 4 of the PMOS-transistor 1.

FIG. 2 shows a further embodiment of the failsafe interface circuitconnecting two circuits 24 and 26 where a selector circuit 28 is notdirectly connected to a control electrode 30 of a PMOS-transistor 32 butoutputs a supply voltage for a control circuit 34 driving the controlelectrode 30 of the PMOS-transistor 32. While the selector circuit 28also receives a signal indicating that the failsafe interface circuit ispowered off via an input terminal 36 and the maximum potential at adrain electrode 40 and the source electrode 42 of the PMOS-transistor 32generated in a maximum generating circuit 38 it does not supply directlythe maximum potential to the control electrode 30 of the PMOS-transistor32. In particular, the selector circuit 28 does not lie directly in thesignal path leading to the control electrode 30 of the PMOS-transistor32. Thus, according to this embodiment the additional circuitrynecessary to achieve failsafety for the interface circuit has no impacton the overall timing performance of the failsafe interface circuit.

A further embodiment aims at the prevention of any backward feed effectsin the interface circuit. In particular, this further embodiment aims atavoiding any backward feed current via parasitic diodes between thedrain electrode or the source electrode and the n-channel of thePMOS-transistor and the prevention of turning on of parasitic thyristorstructures shown in FIG. 20.

FIG. 3 shows an embodiment where a PMOS-transistor 44 is embedded in aninsulating region 46 realized as N-well. Similar to the embodimentsdescribed with respect to FIG. 1 and FIG. 2 the PMOS-transistor 44 isadapted to connect a first circuit 48 and a second circuit 50 in case apotential difference between a control electrode 52 and one of the drainelectrode 54 and the source electrode 56 thereof exceeds a predeterminedthreshold value.

Here, the maximum potential of the drain electrode 54 and the sourceelectrode 56 of the PMOS-transistor 44 generated in a maximum generatingcircuit 58 is not supplied to the control electrode 52 but via aselector circuit 60 to a contact 62 of the insulating region 46embedding the PMOS-transistor 44. Therefore, no backward feed currentflows in parasitic diodes between the drain electrode 54 or the sourceelectrode 56 of the PMOS-transistor 44 and the insulating region 46.Also, a turning on of the parasitic thyristor shown in FIG. 20 can beprevented effectively since the potential of the insulating region 46 isactively controlled to the most positive potential in the failsafeinterface circuit both when the power supply is turned on and when thepower supply is turned off. Therefore, the failsafe interface circuituses the maximum potential that may occur to actively prevent theoccurrence any failure therein.

FIG. 4 shows a further embodiment where the advantages of theembodiments explained above are combined. Here, a maximum potential of adrain electrode 64 and a source electrode 66 of a PMOS-transistor 68generated in a maximum generating circuit 70 is supplied to both acontrol electrode 72 and an insulating region 74 thereof. Therefore thePMOS-transistor 68 can never be turned on in case the interface circuitis powered off and also any backward feed or latchup phenomenon issafely avoided by actively tying the insulating region 74 to the mostpositive potential in the failsafe interface circuit.

The embodiment shown in FIG. 4 comprises two selector circuits 76 and 78used to feedback the maximum potential outputted by the maximumgenerating circuit 70 to the control electrode 72 and the insulatingregion 74, respectively.

Of course it is also possible that the selector circuit 78 feeding thecontrol electrode 72 of the PMOS-transistor 68 is not directly connectedthereto hut to a control amplifier (not shown) that feeds the controlelectrode 72. This allows to eliminate any impact on the timingperformance on the failsafe interface circuit when connecting a firstand a second circuit 80, 82. Further, the first and second selectorcircuits 76, 78 can be combined into a single selector circuit thatconnects both the control electrode 72 and the insulating region 74 ofthe PMOS-transistor 68 to the output of the maximum generating circuit70.

FIG. 5 shows a basic structure of a circuit for generating a maximumpotential from two input potentials that may be used as maximumgenerating circuit. This maximum generating circuit comprises a firstPMOS-transistor 84 and a second PMOS-transistor 86 with the commonelectrode being connected to the output terminal 88 of the maximumgenerating circuit. The control electrode of the first PMOS-transistor84 and the source electrode of the second PMOS-transistor 86 areconnected to a first input terminal 90 of the maximum generatingcircuit. The control electrode of the second PMOS-transistor 86 and thedrain electrode of the first PMOS-transistor 84 are connected to asecond input terminal 92 of the maximum generating circuit.

When the input potential at the first input terminal 90 is higher thanthe input potential at the second input terminal 92 the potential of thecontrol electrode of the second PMOS-transistor 86 is lower than at thesource electrode thereof so that this second PMOS-transistor 86 isturned on. Thus, the potential at the first input terminal 90 issupplied to the output terminal 88.

To the contrary, if the input potential at the second input terminal 92is higher than the input potential at the first input terminal 90 thefirst PMOS-transistor 84 is similarly turned on while the secondPMOS-transistor 86 remains turned off so that the input potential at thesecond input terminal 92 is supplied to the output terminal 88.

FIG. 6 shows a modification of the maximum generating circuit shown inFIG. 5 where a first PMOS-transistor 94 and a second PMOS-transistor 96are embedded in insulating regions adapted to be biased to the maximumpotential at the output terminal 98 of this maximum generating circuit.As outlined above, this allows to avoid any feedback current or latchupphenomenon in the maximum generating circuit and to provide the maximumpotential at the input terminals 100, 102. The maximum generatingcircuits according to FIG. 5 and 6 work as long as the respectivedifference between the potentials at the two input terminals is higherthan a threshold voltage to switch on either PMOS-transistor 84, 94 orPMOS-transistor 86, 96.

However, precautions have to be taken when the potential difference atthe input terminals is lower than this threshold voltage. The reason forthis is that in this case none of the PMOS-transistors will be turnedon. Further, the potential of the insulating regions of thePMOS-transistors is undefined since no current forces the insulatingregions to the highest potential. Also, the potential of the insulatingregions can not drift so far away. It will be limited downwards byparasitic diodes and upwards by the PMOS-transistors because at leastone of them will be turned on when the potential raises more than thethreshold voltage to turn on either of the PMOS-transistors above thepotential at the control electrodes.

This problem is solved by an enhanced version of the maximum generatingcircuits shown in FIG. 5 and 6. This enhanced version of the maximumgenerating circuit is shown in FIG. 7 and comprises four additionalPMOS-transistors 104, 106 and 108, 110 and a current source 112. ThePMOS-transistors 104 and 106 are connected in the same way as thePMOS-transistors 114, 116 corresponding to the PMOS-transistors 84, 86and 94, 96, respectively, to the input terminals 118 and 120 of themaximum generating circuit. Further, the PMOS-transistors 108 and 110are connected in series between these two input terminals 118 and 120,the common electrode of these PMOS-transistors 108 and 110 beingconnected to an output terminal 122. Also, the current source 112 isconnected to both control electrodes of the PMOS-transistors 108 and 110and to the common electrode of the PMOS-transistors 104 and 106.

As long as the potential difference at the input terminals 118 and 120exceeds the threshold potential for turning on either of thePMOS-transistors 114 and 116 the maximum generating circuit shown inFIG. 7 works basically in the same way as the maximum generatingcircuits shown in FIG. 5 and 6. In particular, either of thePMOS-transistors 114 and 104 or 116 and 106 will be turned on and givethe highest potential at the input terminals 118 and 120 to the outputterminal 122 and to the common electrode of the PMOS-transistors 108 and110. Since the largest input potential is supplied to the controlelectrodes of the PMOS-transistors 108 and 110 they are turned off.

If the potential difference at the input terminals 118 and 120 is lowerthan the threshold voltage to turn on either one of the PMOS-transistors114 and 116 or 104 and 106 they will all be turned off. In this case, anode 124 is pulled low by the current source 112 so that thePMOS-transistor 108 or 110 is turned on depending on whichPMOS-transistors 108 or 110 has the highest potential at the electrodeconnected to either of the input terminals 118 and 120. Therefore, alsowhen the potential difference at the input terminals 118 and 120 of themaximum generating circuit shown in FIG. 7 is lower than the thresholdvoltage for turning on either of the PMOS-transistors 114 and 116 or 104and 106 this maximum generating circuit is operable to provide themaximum input potential at the output terminal 122 thereof.

FIG. 8 shows an enhanced version of the maximum generating circuit shownin FIG. 7 where all PMOS-transistors 126 to 136 are embedded ininsulating regions of the N-well type (not shown) that are connected tothe maximum potential derived in this maximum generating circuit.According to this enhanced maximum generating circuit the insulatingregions are always tied to the highest potential. Therefore thepotentials of the insulating regions are always well defined. Also, anybackward feed or latchup phenomenon can be avoided since the parasiticdiodes 138 to 148 between source electrodes or drain electrodes of thePMOS-transistors 126 to 136 and the related insulating regions arecontinuously kept non-conductive. This allows to avoid undesiredvariations in PMOS device parameters, in particular when low voltageprocesses are used.

FIG. 9 shows an embodiment of a selector circuit. Here, aNMOS-transistor 150 has a control electrode connected to a power supplyline 152, a drain electrode connected to a first input terminal 154, anda source electrode connected to an output terminal 156. In addition,there is provided a PMOS-transistor 158 having the control electrodeconnected to the first power supply line 152 and the drain electrodeconnected to the output terminal 156. The source electrode of thisPMOS-transistor 158 is connected to a second input terminal 160 of theselector circuit. An additional PMOS-transistor 162 has its drainelectrode connected to the first input terminal 154 and its sourceelectrode connected to the output terminal 156. A furtherPMOS-transistor 164 has its control electrode connected to the firstpower supply line 152, its source electrode connected to the secondinput terminal 160 and the drain electrode connected to the controlelectrode of the PMOS-transistor 162. The control electrode of thePMOS-transistor 162 and the drain electrode of the PMOS-transistor 164are connected via a NMOS-transistor 166 to a second power supply line168.

When the interface circuit is powered on the selector circuit shown inFIG. 9 connects the first input terminal 154 with the output terminal156. As shown in FIG. 1 and 4, the normal control signal is thensupplied to the control electrode of the PMOS-transistor, whereby thisPMOS-transistor is turned on and connects the circuits linked to thefailsafe interface circuit. In this state also the potential at thefirst power supply line 152 is high so that the NMOS-transistors 150 and166 are turned on. The NMOS-transistor 166 connects the second powersupply line 168 with a low potential to the control electrode of thePMOS-transistor 162 which therefore is also turned on. Therefore, thefirst input terminal 154 is connected via the NMOS-transistor 150 andthe PMOS-transistor 162 to the output terminal 156.

An important advantage of this selector circuit is that NMOS-transistor150 and PMOS-transistor 162 are connected in parallel to connect theinput terminal 154 to the output terminal 156. This increases the commonmode operating range significantly.

The second operation mode of the selector circuit shown in FIG. 9 isrelated to the powered off interface circuit when the potential on thefirst supply line 152 is low. In this state the potential at the secondinput terminal 160 corresponds to the output potential of the maximumgenerating circuit and thus to the maximum potential in the interfacecircuit. Therefore the PMOS-transistor 158 is turned on and thepotential at the second input terminal 160 is supplied to the outputterminal 156 of the selector circuit. For the same reason also thePMOS-transistor 164 is turned on so that the potential at the controlelectrode of the PMOS-transistor 162 corresponds to the maximumpotential in the interface circuit and this PMOS-transistor 162 remainsturned off. The same holds true for the NMOS-transistors 150 and 166since the potential at the respective control electrodes corresponds tothe low potential on the first supply line 152.

FIG. 10 shows a selector circuit with improved failsafe capability.Terminals 170 to 174 receive the maximum of the potential at the secondinput terminal 160 and the VDD potential. Therefore, the maximum of thepotential at the second input terminal 160 and the VDD potential issupplied to the insulating regions of the PMOS-transistors 176 to 180 sothat in any case a turn on of these PMOS-transistors 176 to 180 isprevented. Therefore, the PMOS-transistors 176 to 180 are disconnectedfrom the related control logic in case the interface circuit is poweredoff.

Further, all PMOS-transistors 176 to 180 and NMOS-transistors 182, 184are provided in insulating regions. The insulating regions for theNMOS-transistors 182 and 184 are tied to the potential on a second powersupply line 186 via connections 188 and 190. Further, the insulatingregions of the PMOS-transistors 176 to 180 are tied to the outputpotential of a maximum generating circuit via the terminals 170 to 174.Thus, in the failsafe selector circuit shown in FIG. 10 the potentialsof the insulating regions of the PMOS-transistors 176 to 180 areactively tied to the maximum potential in the failsafe interface circuitand the potentials for the insulating regions of the NMOS-transistors182, 184 are constantly held at ground potential. Therefore, theselector circuit is fully failsafe without any latchup or backward feedphenomenon.

FIG. 11 shows a further embodiment where the failsafe interface circuitis connected to a power supply circuit 192 and an output circuit 194 fordriving an output terminal connected to a transmission line 196. Whileonly a single output circuit is shown in this figure the number ofoutput circuits according to the invention can also be greater than one.This embodiment relates to the transmission of digital data with a hightransfer rate such as the differential transmission and reception ofdigital data.

In particular, a first semiconductor switching circuit 198 is connectedto a first output terminal 200 of the power supply circuit 192 and asecond semiconductor switching circuit 202 is connected to a secondoutput terminal 204 of the power supply circuit 192. Each semiconductorswitching circuit 198, 202 comprises a PMOS-transistor and anNMOS-transistor (shown in dotted lines) operatively coupled across thePMOS-transistor. As outlined above, this allows to increase theswitching range of the semiconductor switching circuits 198, 202 andthus also the applicability of the failsafe interface circuit.

Further, an output terminal of the first semiconductor switching circuit198 is connected to a first input terminal 206 of the output circuit 194and an output terminal of the second semiconductor switching circuit 202is connected to a second input terminal 208 of the output circuit 194.

As outlined above, the power supply circuit 192 comprises an inductance210 and, e.g., one PMOS-transistor 212 and one NMOS-transistor 214 whichare connected to the inductance 210. Through appropriately switching onand off these PMOS- and NMOS-transistors 212, 214 it is possible to setthe duration of a charging phase where energy is transferred from apower source (not shown) to the inductance 210. After this chargingphase the first semiconductor switching circuit 198 and the secondsemiconductor switching circuit 202 are actuated such that at least partof the energy stored in the inductance 210 is transferred to inputterminals 206, 208 of the output circuit 194. Therefore, the potentialat these input terminals 206, 208 varies in dependence of the setting ofthe charging and discharging phase for the inductance 210 and theactuation of the first and second semiconductor switching circuits 198,202, respectively. In addition, the output circuit 194 comprises twoadditional semiconductor switching circuits 216 and 218 connecting theinput terminals 206, 208, respectively, to the output terminal 196 ofthe output circuit 194.

As shown in FIG. 11, a potential at the output terminal 196 of theoutput circuit 194 is fed back via a resistor 220 to the control gatesof the PMOS-transistors 222, 224 comprised in the semiconductorswitching circuits 216 and 218 when the failsafe interface circuit ispowered off. The semiconductor switching circuits 198 and 202, too, areprovided with this failsafe capability.

As is shown in FIG. 11 to each control electrode of the PMOS-transistors226, 228 in the semiconductor switching circuits 198, 202 a selectorcircuit is directly connected, respectively.

FIG. 12 shows a modified embodiment of the output circuit where anadditional PMOS-transistor 230 is inserted into the feedback path fromthe output terminal 196 to the control terminals of the PMOS-transistors222, 224 in the semiconductor switching circuits 216, 218. Also, therelated selector circuit 232 is not directly lying in the signal path tothe control electrodes of these PMOS-transistors 222, 224 but suppliesthe potential at the output terminal 196 of the output circuit 194 aspower supply potential to control, amplifiers 234 and 236 driving thecontrol electrodes of these PMOS-transistors 222, 224 when the failsafeinterface circuit is powered off. Further, when the failsafe interfacecircuit is powered off the selector circuit 232 connects the potentialat the source electrode of PMOS-transistor 238 to a control electrode ofthis PMOS-transistor 238.

As mentioned above, NMOS-transistors are operatively coupled across thePMOS-transistors in the semiconductor switching circuits 198, 202, 216and 218 to enlarge the operative range of these semiconductor switchingcircuits when the failsafe interface circuit is powered on.

Also, as indicated by arrows in FIG. 11 and 12 the different backwardfeed paths in the failsafe interface circuit are cut off at differentpositions, e.g., the semiconductor switching circuits 198 and 202 or thesemiconductor switching circuits 216 and 218.

According to the present invention there exists no particularrestriction where to cut off such backward feed paths. It should benoted that the cut off at the semiconductor switching circuits 212 or198 and 202 has the advantage that no highspeed demands exist for thecontrol of the PMOS- and NMOS-transistors comprised in thesesemiconductor switching circuits 212, 198, 202. In this case precautionsmust be taken to avoid that output terminals, e.g., the output terminals200 and 204 are connected to each other via the common signal linesconnected to the input terminals 206 and 208 and the output circuit 194.Therefore, a preferred way to prevent any backward feed phenomenon inthe interface circuit is to use the circuits according to the inventionat the semiconductor switching circuits 216 and 218 since with thisapproach each input terminal 206 and 208 of the output circuit iscompletely separated from the output terminal 196.

In particular, with respect to the embodiment shown in FIG. 12 this hasno impact on the bandwidth of the failsafe interface circuit since theselector circuit 232 does not lie in the signal line feeding the controlelectrodes of the PMOS-transistors 222, 224 in the semiconductorswitching circuits 216 and 218.

Further, this embodiment has the advantage that the PMOS-transistor 230is only activated during the powered off state and when the outputpotential at the output terminal 196 is raised. Otherwise, thisPMOS-transistor 230 will disconnect the resistor 220 from the internalsupply node to avoid unnecessary power dissipation in case this resistorhas only a small resistance value.

Still further, the additional selector circuit 232 allows to guaranteethe failsafe feature of the PMOS-transistor 238 connecting the internalpower supply to the amplifying circuits 234 and 236 during the poweredon state of the output circuit.

Thus, the control electrodes of the PMOS-transistors 222, 224 follow theraised output signals during powered off states under all circumstancesso that these PMOS-transistors 222, 224 are turned off to avoid anypotential backward feed current or any latchup phenomenon in thefailsafe interface circuit.

FIG. 13 shows a detailed circuit diagram of the output circuit 194. Afirst maximum generating circuit 240 derives the maximum of thepotential on the signal line connecting the PMOS-transistor 230 and theresistor 220 and the potential at the control electrode of thePMOS-transistor 230. This maximum potential is used to bias theinsulating regions of the PMOS-transistor 238 and all PMOS-transistors230, 242, 244 comprised in the control circuits 239, 236 driving thecontrol electrodes of the PMOS-transistors 222, 224 in the semiconductorswitching circuits 216 and 218.

In addition, there is provided a second maximum generating circuit 246that derives the maximum potential at the input terminals 206 and 208 ofthe output circuit 194 and the output terminal 196 thereof. This maximumpotential is used to bias insulating regions of the PMOS-transistors222, 224 in the semiconductor switching circuits 216 and 218. To alsoensure that all NMOS-transistors 248, 250 comprised in the controlcircuits 234, 236 of these PMOS-transistors 222, 224 are failsafe theinsulating regions of these NMOS-transistors 248, 250 are tied to groundpotential.

All input signals to the maximum generating circuits can be summed up inone single maximum generating circuit and distributed to all involvedPMOS-transistors. However, in some instances it is beneficial toseparate the considered potentials for the different insulating regionssince the higher the potential of the insulating regions is incomparison to the drain and source electrodes of the PMOS-transistorsthe weaker the PMOS-transistors are due to an increased thresholdvoltage. Therefore, when the output circuit works far below the supplypotential it is beneficial to let the insulating regions follow thislower potential level.

Another embodiment being related to the prevention of failures ininterface circuits due to noise and ripples is shown in FIG. 14. Toovercome this problem, it is necessary to achieve an enhanced decouplingof the potentials at the input terminals 206 and 208 of the outputcircuit 194, in particular when the decouplings are situated off chipafter the output buffers. Here decoupling means a filtering process forthe signals being transferred by the interface circuit.

One approach to overcome the problem with power fed noise is to cut theinternal supply connections from the previous circuit to the inputterminals 206, 208 of the output circuit 194 and carry out thedecoupling or filtering separately from the interface circuit. Oneoption is to embody the previous circuit and the internal supplyconnections connected thereto on a single integrated circuit and to leadthese internal supply lines off the integrated circuit onto the capsulelevel or the printed circuit board level to carry out thedecoupling/filtering for the noise and ripple components in the suppliedpotentials.

After the decoupling the supplied potentials are again fed back onto theintegrated circuit. This embodiment of the invention requires at leastone additional pin to get onto the capsule level or the printed circuitboard level and then hack onto the integrated circuit with essentiallynoise free potentials on the supply lines to the input terminals 206,208 of the output circuit 194.

As outlined above the number of output circuit is not restricted to onebut can also be greater than one. In this case not only care has to betaken with respect to noise and ripple components but also with respectto the strict separation of the different output circuits from eachother so as to avoid any interaction between the different outputcircuits.

This separation function requires a special arrangement shown in FIGS.14 to 16. The major difference to the embodiments outlined above is thatduring power off when it is desirable to have the outputs freelyfloating they are completely independent from the supply lines to theinput terminals 206, 208 so that even these supply lines can freelyfloating during power off.

As is shown in FIG. 14, to achieve this strict disconnection everyoutput circuit is provided with a semiconductor switching means 252 ofwhich the first terminal is connected to the first input terminal 206 ofthe output circuit 194. Further, the second terminal is connected to theoutput terminal 196 of the output circuit 194. A maximum generatingcircuit 254 receives at its input terminals the potentials at the inputterminal and the output terminal of the output circuit. The maximumpotential thereof is supplied to the insulating region of thesemiconductor switching means 252 and also to one input terminal of afurther maximum generating circuit that in addition receives thepotential on the power supply line of the output circuit. The outputpotential of the maximum generating circuit 256 is supplied to aselector circuit 258 which is connected to the control electrode of anNMOS-transistor 260. The first electrode of the NMOS-transistor 260 isconnected to the input terminal 262 of a driving circuit 264, 266driving the semiconductor switching means 252. Further, the secondelectrode of the NMOS-transistor is connected to the second supply lineof the output circuit, i.e. to ground.

As is shown in FIG. 14, there is further provided a PMOS-transistor 268of which the control electrode is connected to the power supply line ofthe output circuit 194, the first electrode is connected to the outputof the maximum generating circuit 256 and the second electrode isconnected to the output terminal 270 of the driving circuit 264, 266.The output of the selector circuit 258 is also connected to a controlelectrode of a PMOS-transistor 272 of which the first terminal isconnected to the power supply line of the output circuit 194 and thesecond terminal is connected to the first terminal of a PMOS-transistor264 in the driving circuit 264, 266.

As outlined above, the circuit shown in FIG. 14 achieves a strictdisconnection of the different signal lines in the output circuit 194.Firstly, the maximum generating circuit 254 derives the maximumpotential at the power supply line connected to the first input terminal206 and the output terminal 196 which is then used to bias theinsulating region of the semiconductor switching means 252 as outlinedabove.

Further, the generated maximum, potential is also compared to thepotential on the power supply line in the maximum generating circuit 256so as to achieve the maximum potential in the output circuit. Thisoverall maximum potential is then fed back via a selector circuit 258 toa control electrode of an NMOS-transistor 260. Therefore, during poweroff this NMOS-transistor 260 will be turned on so as to connect theinput terminal 262 of the driving circuit 264, 266 to the second supplypotential, i.e. to ground.

Still further, during power off the potential at the control electrodeof the PMOS-transistor 268 is lower than the maximum potential appliedto the first terminal thereof so that this PMOS-transistor 268 serves totie the output terminal 270 of the driving circuit 264, 266 to themaximum potential in the output circuit 194. Therefore, thesemiconductor switching means 252 is safely turned off to always achievea perfect disconnection between the line connected to the input terminal206 and the line connected to the output terminal 196 during power offof the output circuit. In addition, the PMOS-transistor 272 allows todisconnect the power supply line from the driving circuit 264, 266during power off of the output circuit.

FIG. 15 shows a modified embodiment according to FIG. 14 which isadapted to a push-pull output circuit. There is provided a furthersemiconductor switching means 274 connected to the second input terminal208 of the output circuit, and an additional maximum generating circuit276 deriving the maximum potential at this input terminal 208 and theoutput terminal 196 of the output circuit. This maximum potential is fedback to the insulating regions of the semiconductor switching means 274and also supplied to a maximum generating circuit 278 that receives theoutput potential of the maximum generating circuit 254. The maximumpotential of the received input potentials is supplied to the maximumgenerating circuit 256.

In addition to the circuit elements described with respect to FIG. 14there is provided an additional NMOS-transistor 280 connected to aninput terminal 282 of a driving circuit 284, 286 driving thesemiconductor switching means 274. Also, a PMOS-transistor 288 isconnected with its first electrode to the output terminal 290 of thedriving circuit 284, 286 and with its second electrode to the output ofthe maximum generating circuit 256. The control electrode of thePMOS-transistor 288 is connected to the first supply line, i.e. the samepotential as the control electrode of the PMOS-transistor 268. APMOS-transistor 292 is connected with its first electrode to the powersupply line of the output circuit, with its second electrode to thefirst electrode of a PMOS-transistor 284 of the driving circuit 284,286, and with its control electrode to the output of the selectorcircuit 258.

The functionality of the circuit shown in FIG. 15 basically correspondsto the functionality explained with respect to FIG. 14. Of particularimportance is the simultaneous tying of the input terminals 262, 282 ofboth driving circuits 264, 266 and 284, 286 to ground viaNMOS-transistors 260 and 280 during power off. Also, at the same timethe output terminals 270, 290 are tied to the maximum potential in theoutput circuit via PMOS-transistors 268, 288 so as to safely guarantee aturned off state of the semiconductor switching circuits 252 and 274.Therefore, both the signal lines connected to the input terminals 206and 208 of the output circuit and also the output lines are strictlydisconnected which allows for an independent free floating of theselines during power off.

While according to FIG. 15 the insulating regions for the differentPMOS-transistors are separated they can as well be supplied in a commonmode, as is shown in FIG. 16. Further, the maximum generating circuit254 may be substituted by resistors in case the potential difference atthe input terminal 206, 208 of the differential output circuits issmall, e.g., smaller than 2×Vd.

FIG. 17 shows an output circuit of the differential type. This outputcircuit comprises two output terminals 298 and 302 and two feedbackresistors being connected such that the mean value of the outputpotentials created by the feedback resistors gives the potential to biasthe insulating regions of PMOS-transistors 294, 300, 304 and 308 in theoutput circuit of the differential type.

The connection of the different PMOS-transistors 294, 300, 304 and 308is such that the two output terminals 292 and 302 of this output circuitcan relate to a pair of signaling wires for the transmission of digitaldata according to signaling concepts using differential signaling likedifferential positive emitter coupled logic DPECL, low voltagedifferential signaling LVDS and grounded low voltage differentialsignaling GLVDS.

Therefore, according to the invention there is provided a failsafeinterface circuit for providing differential signals while keepingdifferential. voltages across pairs of signal wires low without anyadverse effect on the quality of data transmission. Since thisdifferential signaling approach leads only to a low power dissipationper unit area an integration into a single CMOS-circuit is possible incase precautions according to the invention are taken to avoid anybackward feed phenomenon or latchup phenomenon in the integratedinterface circuit.

Another advantage of the output circuit of the differential type shownin FIG. 17 is that the voltage across the output terminals 298 and 302may float with respect to the voltage across the input terminals of thepower supply circuit shown in FIG. 11. This means that a voltage acrossthe input terminals of the power supply circuit and the output terminals298 and 302 will not lead to a current flowing from the respective inputterminals to the respective output terminals.

Therefore, the operation of the power supply circuit connected by theinventive failsafe interface circuit to the output circuit of thedifferential type is fully independent from the application of suchvoltages. Thus, the failsafe interface circuit according to theinvention enables the prevention of output signals not conforming todifferential signalling concepts.

While all circuits have been explained with respect to PMOS-transistorsembedded in insulating regions realized as N-wells, the invention alsoapplies to cases corresponding to substrates of the N-type and usinginsulating regions realized as P-wells. Here, care is taken about theNMOS-transistors in the same way as explained above with respect toPMOS-transistors. No particular care has to be taken with respect toPMOS-transistors. As outlined above, the substrate will be connected tothe most positive potential in case the interface circuit is poweredoff.

Of course both approaches relating to a substrate of the P-type and asubstrate of the n-type may be combined for twin well processes andlightly doped substrates of the p-type which may be treated in the sameway as the substrate of the p-type having insulating regions realized asn-wells.

What is claimed is:
 1. Interface circuit, comprising:at least onesemiconductor switching means (44; 68) having a first link terminal (54;64), a second link terminal (56; 66) and a control terminal (52; 72),said first link terminal (54; 64) being connected to a first circuitmeans (48; 80), said second link terminal (56; 66) being connected to asecond circuit means (50; 82), and said semiconductor switching means(44; 68) being adapted to connect said first circuit means (48; 80) tosaid second circuit means (50; 82) when a potential difference betweensaid control terminal (52; 72) and one of said first link terminal (54;64) and said second link terminal (56; 66) exceeds a predeterminedthreshold value, and failure prevention means (60, 58; 70, 76, 78)adapted to apply the maximum potential of said first link terminal (54;64) and said second link terminal (56, 66) to said control terminal (52;72) in case said interface circuit is powered off, wherein said failureprevention means (60, 58; 70, 76, 78) comprises:a first maximumgenerating means (58; 70) adapted to output the maximum potential ofsaid first link terminal (54; 64) and said second link terminal (56,66), and a first selector means (60) connected to said first maximumgenerating means (58, 70) and being adapted to select the output thereofas power supply potential of a control amplifier feeding said controlterminal (52; 72)in case said interface circuit is powered off. 2.Interface circuit according to claim 1, whereinsaid semiconductorswitching means (44; 68) of a first conductivity type (P), and saidfailure prevention means (60, 58; 70, 76, 78) is further adapted toapply the maximum potential of said first link terminal (54; 64), saidsecond link terminal (56; 66) to an insulating region (46; 74) in casesaid interface circuit is powered off.
 3. Interface circuit according toclaim 2, whereinsaid failure prevention means (70, 76, 78) comprises asecond selector means (78) connected to said first maximum generatingmeans (70) and being adapted to select the output thereof as potentialsupplied to said control terminal (72) when said interface circuit ispowered off.
 4. Interface circuit according to claim 3, wherein saidfirst maximum generating means (12; 38; 58; 70) comprises:a firsttransistor switching means (84; 94) of said first conductivity type (P)with a control electrode being connected to a first input terminal (90;100) of said first maximum generating means (12; 38; 58; 70), a firstelectrode being connected to a second input terminal (92; 102) of saidfirst maximum generating means (12, 38; 58; 70), and a second electrodebeing connected to an output terminal (88; 98) of said first maximumgenerating means (12; 38; 58; 70), and a second transistor switchingmeans (86; 96) of said first conductivity type (P) having a controlelectrode being connected to said second input terminal (92; 102) ofsaid first maximum generating means (12; 38; 58; 70), a first electrodebeing connected to said second electrode of said first transistorswitching means (84; 94), and a second electrode being connected to saidfirst input terminal (90; 100) of said first maximum generating means(12; 38; 58; 70), wherein said output terminal (88; 98) of said firstmaximum generating means (12; 38; 58; 70) is connected to said secondelectrode of said first transistor switching means (84; 94) and saidfirst electrode of said second transistor switching means (86; 96). 5.Interface circuit according to claim 4, wherein said first transistorswitching means (94) and said second transistor switching means (96) areprovided in insulating regions adapted to be biased to a potential atsaid output terminal (98) of said first maximum generating means (12;38; 58; 70) when said interface circuit is powered off.
 6. Interfacecircuit according to claim 4, wherein said first maximum generatingmeans (12; 38; 58; 70) further comprises:a third transistor switchingmeans (104; 126) of said first conductivity type (P) with a controlelectrode being connected to said first input terminal (118) of saidfirst maximum generating means (12; 38; 58; 70), a first electrode beingconnected to said second input terminal (120) of said first maximumgenerating means (12; 38; 58; 70), and a second electrode connected to acurrent source means (112), and a fourth transistor switching means(106; 128) of said first conductivity type (P) having a controlelectrode being connected to said second input terminal (120) of saidfirst maximum generating means (12; 38; 58; 70), a first electrode beingconnected to said second electrode of said third transistor switchingmeans (104; 126), and a second electrode being connected to said firstinput terminal (118) of said first maximum generating means (12; 38; 58;70), said first electrode also being connected to said current sourcemeans (112), a fifth transistor switching means (108; 130) of said firstconductivity type (P) with a control electrode being connected to saidcurrent source means (112), a first electrode being connected to saidsecond input terminal (120) of said first maximum generating means (12;38; 58; 70), and a second electrode being connected to said outputterminal (122) of said first maximum generating means (12; 38; 58; 70),and a sixth transistor switching means (110; 132) of said firstconductivity type (P) having a control electrode being connected to saidcurrent source means (112), a first electrode being connected to saidsecond electrode of said fifth transistor switching means (108; 130),and a second electrode being connected to said first input terminal(118) of said first maximum generating means (12; 38; 58; 70). 7.Interface circuit according to claim 6, wherein said third, fourth,fifth and sixth transistor switching means (104, 106, 108, 110; 126,128, 130, 132) are provided in insulating regions adapted to be biasedto a potential at said output terminal (122) of said first maximumgenerating means (12; 38; 58; 70) when said interface circuit is poweredoff.
 8. Interface circuit according to claim 1, wherein said firstcircuit means (8; 24; 48; 80) is power supply means (92) for supplyingpower via said at least one semiconductor switching means (198; 202) tosaid second circuit means (10; 26; 50; 82).
 9. Interface circuitaccording to claim 8, wherein said second circuit means (10; 26; 50; 82)is an output means (194) for driving a load.
 10. Interface circuitaccording to claim 9, wherein said power supply means (192) and saidoutput means (194) are coupled bya first semiconductor switching means(198) provided with said failure prevention means, said firstsemiconductor switching means (198) connecting a first output terminal(200) of said power supply means (192) and a first input terminal (206)of said output means (194), and a second semiconductor switching means(202) provided with said failure prevention means, said secondsemiconductor switching means (202) connecting a second output terminal(204) of said power supply means (192) and a second input terminal (208)of said output means (194).
 11. Interface circuit according to claim 10,wherein said power supply means (192) further comprises:a reactancemeans (210) adapted to temporarily store energy and being connected tosaid first and second output terminal (200, 204) of said power supplymeans (192), and charging switching means (212, 214) being connected tosaid reactance means (210) and being adapted to provide a charging phasein which energy is supplied to said reactance means (210) from a powersource and a discharging phase during which at least part of said energystored in said reactance means (210) is discharged to said first andsecond output terminal (200, 204) of said power supply means (192). 12.Interface circuit according to claim 11, wherein said charging switchingmeans (212, 214) comprises a third semiconductor switching means (212)provided with said conduction prevention means or said failureprevention means.
 13. Interface circuit according to claim 12, whereinsaid output means (194) comprises:a third semiconductor switching means(216; 222) with a first link terminal, a second link terminal and acontrol terminal and comprising a failure prevention means adapted toapply the maximum potential of said first link terminal and said secondlink terminal to said control terminal in case said interface circuit ispowered off or a failure prevention means adapted to apply the maximumpotential of said first link terminal and said second link terminal toan insulating region of said fourth semiconductor switching means (216;222) in case said interface circuit is powered off, and a fourthsemiconductor switching means (218; 224) with a first link terminal, asecond link terminal and a control terminal and comprising a failureprevention means adapted to apply the maximum potential of said firstlink terminal and said second link terminal to said control terminal incase said interface circuit is powered off or a failure prevention meansadapted to apply the maximum potential of said first link terminal andsaid second link terminal to an insulating region of said fifthsemiconductor switching means (218; 224) in case said interface circuitis powered off, where said third semiconductor switching means (216;222) and said fourth semiconductor switching means (218; 224) areconnected to an output terminal (196) of said output means and a firstand a second input terminal (206, 208) of said output means,respectively.
 14. Interface circuit according to claim 13, wherein apotential at said output terminal (196) is supplied via a resistor means(220) and a failure prevention means to a control terminal of said thirdsemiconductor switching means (216) and said fourth semiconductorswitching means (218) during power off of said interface circuit. 15.Interface circuit according to claim 13, whereina tenth transistorswitching means (238) of said first conductivity type (P) adapted tosupply a first supply potential (VDD) to first driving circuit means(234, 236) driving said third semiconductor switching means (216) andsaid fourth semiconductor switching means (218) when said output meansis powered on, and an eleventh transistor switching means (230) of saidfirst conductivity type (P) adapted to supply said potential at saidoutput terminal (196) of said output means via said resistor means (220)as supply potential to said first driving circuit means (234, 236) ofsaid third semiconductor switching means (216) and said fourthsemiconductor switching means (218), respectively, when said outputmeans is powered off.
 16. Interface circuit according to claim 15,wherein said third and fourth semiconductor switching means (216, 218;222, 224) comprise p-channel MOSFETs of the first conductivity type (P).17. Interface circuit according to claim 16, wherein there is provided asecond maximum generating means (240) adapted to bias insulating regionsof transistor switching means of said first conductivity type (P) insaid interface circuit not comprised in said third and fourthsemiconductor switching means (216, 218) to a maximum potential of asupply potential and said potential at said output terminal (196) ofsaid output means.
 18. Interface circuit according to claim 17, whereinthere is provided a third maximum generating means (246) adapted to biasinsulating regions of transistor switching means of said firstconductivity type (P) comprised in said third and fourth semiconductorswitching means (216, 218) to a maximum potential of said inputterminals (206, 208) and said potential at said output terminal (196) ofsaid interface circuit.
 19. Interface circuit, comprising:at least onesemiconductor switching means (44; 68) having a first link terminal (54;64), a second link terminal (56; 66), and a control terminal (52; 72),said first link terminal (54; 64) being connected to a first circuitmeans (48; 80), said second link terminal (56; 66) being connected to asecond circuit means (50; 82), and said semiconductor switching means(44; 68) being adapted to connect said first circuit means (48; 80) tosaid second circuit means (50; 82) when a potential difference betweensaid control terminal (52; 72) and one of said first link terminal (54;64) and said second link terminal (56; 66) exceeds a predeterminedthreshold value, and failure prevention means (60, 58; 70, 76, 78)adapted to apply the maximum potential of said first link terminal (54;64) and said second link terminal (56, 66) to said control terminal (52;72) in case said interface circuit is powered off, wherein said failureprevention means (60, 58; 70, 76, 78) comprises:a first maximumgenerating means (58; 70) adapted to output the maximum potential ofsaid first link terminal (54; 64) and said second link terminal (56,66), and a first selector means (60) connected to said first maximumgenerating means (58, 70) and being adapted to select the output thereofas power supply potential of a control amplifier feeding said controlterminal (52; 72) in case said interface circuit is powered off, andsaid first selector means (14; 28; 60; 76; 78) comprises:a firsttransistor switching means (150; 182) of a second conductivity type (N)having a control electrode being connected to a first power supply line(152), a first electrode being connected to a first input terminal (154)of said first selector means (14; 28; 60; 76; 78), and a secondelectrode being connected to an output terminal (156) of said firstselector means, and a seventh transistor switching means (158; 176) of afirst conductivity type (P) having a control electrode being connectedto a first power supply line (152), a first electrode being connected tosaid output terminal (156) of said first selector means (14; 28; 60; 76;78), and a second electrode being connected to a second input terminal(160) of said first selector means (14; 28; 60; 76; 78), an eighthtransistor switching means (162; 178) of said first conductivity type(P) having a control electrode, a first electrode being connected tosaid first input terminal (154) of said first selector means (14; 28;60; 76; 78), and a second electrode being connected to said outputterminal (156) of said selector means (14; 28; 60; 76; 78), a ninthtransistor switching means (164; 180) of said first conductivity type(P) having a control electrode being connected to said first powersupply line (152), a first electrode being connected to said controlelectrode of said eighth transistor switching means (162; 178), and asecond electrode being connected to said second input terminal (160) ofsaid first selector means (14; 28; 60; 76; 78), and a second transistorswitching means (166; 184) of said second conductivity type (N) having acontrol electrode being connected to said first power supply line (152),a first electrode being connected to said control electrode of saideighth transistor switching means (162; 178), and a second electrodebeing connected to a second power supply line (168; 186).
 20. Interfacecircuit according to claim 19, wherein said seventh, eighth and ninthtransistor switching means (176, 178, 180) of said first conductivitytype (P) are provided in an insulating region, respectively, and adaptedto be biased to an externally generated bias potential (AN) when saidinterface circuit is powered off.
 21. Interface circuit according toclaim 20, wherein said first and second transistor switching means (182,184) of said second conductivity type (N) are provided in an insulatingregion, respectively, and adapted to be biased to a potential of saidsecond power supply line (186) when said interface circuit is poweredoff.
 22. Interface circuit, comprising:at least one semiconductorswitching means (44; 68) having a first link terminal (54; 64), a secondlink terminal (56; 66), and a control terminal (52; 72), said first linkterminal (54; 64) being connected to a first circuit means (48; 80),said second link terminal (56; 66) being connected to a second circuitmeans (50; 82), and said semiconductor switching means (44; 68) beingadapted to connect said first circuit means (48; 80) to said secondcircuit means (50; 82) when a potential difference between said controlterminal (52; 72) and one of said first link terminal (54; 64) and saidsecond link terminal (56; 66) exceeds a predetermined threshold value,and failure prevention means (60, 58; 70, 76, 78) adapted to apply themaximum potential of said first link terminal (54; 64) and said secondlink terminal (56, 66) to said control terminal (52; 72) in case saidinterface circuit is powered off, wherein said failure prevention means(60, 58; 70, 76, 78) comprises:a first maximum generating means (58; 70)adapted to output the maximum potential of said first link terminal (54;64) and said second link terminal (56, 66), and a first selector means(60) connected to said second maximum generating means (58, 70) andbeing adapted to select the output thereof as power supply potential ofa control amplifier feeding said control terminal (52; 72) in case saidinterface circuit is powered off, and said first circuit means (8; 24;48; 80) is power supply means (92) for supplying power via said at leastone semiconductor switching means (198; 202) to said second circuitmeans (10; 26; 50; 82), said second circuit means (10; 26; 50; 82) is anoutput means (194) for driving a load, and the output means comprises:afifth semiconductor switching means (252) having a first terminalconnected to a first input terminal (206) of said output means andhaving a second terminal connected to an output terminal (196) of saidoutput means, and a fourth maximum generating means (254) adapted tobias insulating regions in said fifth semiconductor switching means(252) to a maximum potential of said potential at said first inputterminal (206) and said output terminal (196) of said output means. 23.Interface circuit according to claim 22, which further comprises:a fifthmaximum generating means (256) adapted to generate a maximum potentialof said output potential of said fourth maximum generating means (254)and a power supply potential of said output means, a third selectormeans (258) adapted to provide the output potential of said fifthmaximum generating means (256) to a control electrode of a thirdtransistor switching means (260) of said second conductivity type (N)having its first electrode connected to an input terminal (262) of asecond driving circuit means (264, 266) driving said third semiconductorswitching means (252) and having its second electrode connected to asecond supply line of said output means, and a twelfth transistorswitching means (268) of said first conductivity type (P) adapted toconnect the output terminal (270) of said second driving circuit means(264, 266) to said output potential of said fifth maximum generatingmeans (256).
 24. Interface circuit according to claim 23, wherein thereis further provided a thirteenth transistor switching means (272) ofsaid first conductivity type (P) adapted to disconnect said seconddriving circuit means (264, 266) from said power supply line duringpower off of said output means.
 25. Interface circuit according to claim23, wherein there is further provided a sixth semiconductor switchingmeans (274) having a first terminal connected to said output terminal(196) of said output means and having a second terminal connected tosaid second input terminal (208) of said output means, respectively. 26.Interface circuit according to claim 25, wherein there is furtherprovided a sixth maximum generating means (276) adapted to biasinsulating regions in said sixth semiconductor switching means (274) toa maximum potential of said potential at said second input, terminal(208) and said output terminal (196) of said output means.
 27. Interfacecircuit according to claim 26, wherein there is further provided aseventh maximum generating means (278) adapted to supply the maximumoutput potentials of said fourth maximum generating means (254) and saidsixth maximum generating means (276) to said fifth maximum generatingmeans (256).
 28. Interface circuit according to claim 27, wherein saidthird selector means (258) is also adapted to supply the output of saidfifth maximum generating means (256) to a control electrode of a fourthtransistor switching means (280) of said second conductivity type (N)having a first electrode connected to an input terminal (282) of a thirddriving circuit means (284, 286) driving said sixth semiconductorswitching means (274) and having a second terminal connected to saidsecond supply line.
 29. Interface circuit according to claim 28, whereinthere is further provided a fourteenth transistor switching means (288)of said first conductivity type (P) adapted to connect said outputterminal (290) of said third driving circuit means (284, 286) to saidoutput terminal of said fifth maximum generating means (256). 30.Interface circuit according to claim 29, wherein there is furtherprovided a fifteenth transistor switching means (292) of said firstconductivity type (P) adapted to disconnect said third driving circuitmeans (284, 286) from said power supply line during power off of saidoutput means.
 31. Interface circuit according to claim 22, wherein saidoutput means (194) is a differential output circuit comprising:asixteenth transistor switching means (294) of said first conductivitytype (P) with a control electrode, a first electrode connected to afirst input terminal (296), and a second electrode connected to a firstoutput terminal (298) of said output means (194), a seventeenthtransistor switching means (300) of said first conductivity type (P)with a control electrode, a first electrode connected to said firstinput terminal (296), and a second electrode connected to a secondoutput terminal (302) of said output means (194), an eighteenthtransistor switching means (304) of the first conductivity type (P) witha control electrode, a first electrode connected to said first outputterminal (298) of said output means (194), and a second electrodeconnected to a second input terminal (306), and a nineteenth transistorswitching means (308) of the first conductivity type (P) with a controlelectrode, a first electrode connected to said second output terminal(302) of said output means (194), and a second electrode connected tosaid second input terminal (306) of said output means (194). 32.interface circuit according to claim 31, wherein each insulating regionof said twelfth to fifteenth transistor switching means (294, 300, 304,308) is biased to an average potential of said first and second outputterminal (298, 302) of said output means (194).
 33. Interface circuitaccording to claim 31, wherein each of said transistor switching meansof the first conductivity type (P) is a p-channel MOSFET transistor. 34.Interface circuit according to claim 31, wherein each of said transistorswitching means of the second conductivity type (N) is an n-channelMOSFET transistor.
 35. Interface circuit according to claim 31, whereineach of said insulating regions is an N-well.
 36. Failure preventionmethod for an interface circuit comprising at least one semiconductorswitching means (1) having a first link terminal (2), a second linkterminal (4), and a control terminal (6), said semiconductor switchingmeans (1) being activated when a potential difference between saidcontrol terminal (6) and one of said first link terminal (2) and saidsecond link terminal (4) exceeds a predetermined threshold value,comprising the step:apply the maximum potential of said first linkterminal (2) and said second link terminal (4) to a control amplifierfeeding said control terminal (6) of said semiconductor switching means(1) when said interface circuit is powered off.
 37. Failure preventionmethod according to claim 36, further comprising the step of applyingthe maximum potential of said first link terminal (2) and said secondlink terminal (4) to an insulating region of said semiconductorswitching means (1) when said interface circuit is powered off.